基本信息:
谢永瑞，研究员，博士
半导体电子设计工程专业
个人教育与工作简历：
1986.09 – 1990.06：清华大学电机系学士
1990.09 – 1992.06：清华大学电机所系统组硕士
1992.09 – 1997.12：清华大学电机所电子系统组博士
1998.10 – 2002.10：国科会芯片设计中心，设计服务组
2002.10 – 2005.11：瀚邦电子股份有限公司，设计部，经理
2005.12 - 2010.2：创意电子股份有限公司，设计服务处，部经理
2010.3 – 2013.9：擎泰电子股份有限公司，设计部，处长
2013.9 –至今：创意电子股份有限公司，设计服务处，处长
研究方向：
数字与混合电路可测试性设计方法
代表性论文及专着：
1.Shieh,Yeong-Ruey and Wu, Cheng-Wen,“Concurrent error detection of CMOS digital and analog faults”,Europe Test Conference (ETC) 93, 1993/05/19
2.Shieh,Yeong-Ruey and Wu, Cheng-Wen,“DC control and observation structures for analog circuits”,Asian Test Symposium (ATS) 1995, IEEEDeign & Test,P.120-1 26, 1995/12/23
3.Shieh,Yeong-Ruey and Wu,Cheng-Wen,“Logic testing of switch-level faults for CMOS unate networks”,7th International Symposium on IC technology,System and Application (ISIC 97), P.212-215,1997/12/01
4.Shieh,Yeong-Ruey and Wu, Cheng-Wen,“Design of CMOS PSCD circuits and checkers for stuck-at and stuck-on faults”,VLSI Design, P.357-372, Vol. 5, No.4, 1998/01/01
5.Shieh,Yeong-Ruey and Wu, Cheng-Wen,“Control and Observation Structures for Analog Circuits”, IEEE Design & Test of Computers, P.56-64, April-June 1998
专利：
Data transmitting device and system for portable device and method thereof
Publication number: 201300119046
Type: Application
Filed: July 15, 2011
Publication date: January 17, 2013
Inventors: Yeng-Ruey Shieh, Shih-Keng Cho, Hsu-Pin Liu, Wei-Shu Hsu, Chi-Han Lin, Yu-Shiang Wang
